1. Field of the Invention
The present invention relates to a VLC(Variable Length Code) decoder.
2. Discussion of the Related Art
In general, the VLC(Variable Length Code), sometimes called as the Hoffmann code, is an optimal code used in a high speed transmission system, to which statistical characteristics of a data is applied, in a manner that once the statistical characteristics of a data are known, the shorter code word is designated, the more frequent video data are generated, and the longer code word is designated, the less frequent video data are generated. If appropriate code words are designated to all possible video data by such a method, an average bit length of code words can be compressed shorter than an originally intended average bit length. Therefore, this VLC is a lossless coding method frequently used for a data of which statistical characteristics are well known.
This VLC is actually employed in systems which require a technique for compressing a video data, such as MPEG 1(Moving Picture Expert Group 1), NEPEG 2(Moving Picture Expert Group 2) and HDTV(High Definition Television) for denser compression of the data. Since faster variable length code decoders come into demand as the time goes by, structures using a PLA(Programmable Logic Array)-based architecture, rather than a tree-based architecture, have been suggested, most of which are focused on reduction of the longest delay time in the variable length code decoder. However, in case the complicated variable length code decoder forms a function block, together with circuits connected thereto and around it in a system, such as NFPEG 1, MPEG 2, or HDTV, the speed of this function block is dependent on the longest delay time existing in parts connecting the variable length code decoder and the circuits around it. Therefore, in providing a variable length code decoder which will form one function block connected with circuits around it in a system, such as MPEG 1, MPEG 2, or HDTV, not only the longest delay time of the variable length code decoder itself, but also the longest delay time existing in parts connecting the variable length code decoder and the circuits around it, should be taken into account. As shown in FIG. 1, an encoded code word(or a data) received at an input buffer 2 is decoded by a data path 3 having a variable length code decoder included therein under the control of a control logic part 1, and produced through an output buffer 4. As seen from above, a variable length code decoder(VLC) in general forms a function block, together with circuits around it connected thereto. In this instant, although an output of the VLC table may be directly stored in an input buffer in another function block, in most cases, the output is applied to one or more circuits around it, or stored in the input buffer of another function block only after being converted into another suitable form in another function block.
A prior art device for decoding a variable length code according to a prior art(U.S. Pat. No. 5,245,338) will be explained with reference to FIG. 2. FIG. 2 illustrates a block diagram showing a prior art variable length code decoder.
Referring to FIG. 2, the prior art variable length code decoder includes an input buffer 201, a first latch part 202, a first barrel shifter 203, a second latch part 204, a second barrel shifter 205, a VLC table 206, a first latch 207, a control signal generating part 208 and an output buffer 209. The first latch part 202 includes a second latch 202a and a third latch 202b, the second latch part 204 includes a fourth latch 204a and a fifth latch 204b. The control signal generating part includes an adder 208a and a sixth latch 208b.
Referring to FIG. 2, the VLC table 206 having random logic decodes successive code words continuously to produce decoded code words of a fixed length in response to a read signal of a fixed symbol clock rate. The first latch part 202 and the barrel shifter 203 appropriately interfaces the input buffer 201 with the second latch part 204. The input buffer 201 stores a serial bit stream of code words having variable lengths received from a data channel into a data segment having a fixed length. The control signal generating part 208 produces 16 bit sized data in parallel in response to the read signal from the sixth latch 208b. The VLC table 206 produces a bit length of a code word of an unknown bit length and a decoded code word having the bit length and supplies its output to the latch 207 and the output buffer 209, respectively. The output side of the second barrel shifter 205 provides a decoding window to the VLC table 206 and is controlled by bit lengths of the decoded code words accumulated in the first latch 207 up to a prior clock of the present clock. Code words of variable lengths are provided from the latches 204a and 204b to the second barrel shifter 205. Each of the latches 204a and 204b has a bit capacity at least the length of the longest code word. The second latch part 204 therefore provides successive bits having at least two variable length code words. An output side of the second barrel shifter 205 is connected to an input side of the VLC table 206, to apply bits of the longest code word to be decoded of the successive bits of a length two times the longest code word stored in the fourth latch 204a and the fifth latch 204b wile input data are provided from the input buffer 210 to the first latch part 202 and the first barrel shifter 203. The VLC table 206 applies the length of the code word received from the second barrel shifter 205 to the first latch 207, and the decoded code word to the output buffer 209. At a clock next to the present clock, the second barrel shifter 205 is controlled by the lengths of the code words decoded up to a prior clock received from the first latch 207. Accordingly, an output window of the second barrel shifter 205 is shifted by the bit lengths of the code words decoded up to a prior clock received from the first latch 207, to start from the first bit of a code word to be decoded, newly. Since all the bits in the fourth latch 202a are transformed at all clocks, the fifth latch 204b is filled again with a corresponding bit stream from the first barrel shifter 203 which has an interfacing function during a cycle corresponding to each clock. That is, a successive bit stream starting from the first bit of a decoded code word appears on the input side of the second barrel shifter 205. And, although first barrel shifter 203 provides a bit stream to the fifth latch 204b, this bit stream is not included in the longest delay time because this bit stream is applied to the fifth latch 204b, directly. Thus, the bit stream of code words decoded at a prior clock appeared on the input side of the second barrel shifter 205 should be up-dated during a cycle corresponding to each clock without fail. As explained, an input to the fifth latch 204b is provided from the interfacing first barrel shifter 203. A code word is provided to an input side of the interfacing first barrel shifter 203 from the two successive latches 202a and 202b having a capacity for the longest code word length and the input buffer 201. The interfacing second and third latches 202a and 202b have a bit capacity for the longest code word length which may be produced by the input buffer 201. The output of the first barrel shifter 203 is controlled both by the length of the code word decoded from the output of the VLC table 206 and the output of the adder 208a which adds up the lengths of the code words decoded up to a prior clock of the present clock received from the sixth latch 208a in the control signal generating part 208. The output of the first barrel shifter 203 is shifted according to bit lengths of the decoded code words added up by the adder 208a, to produce outputs of the second barrel shifter 205 and the successive bit streams. A series of bit sequence from the interfacing first barrel shifter 203 appears on the input side of the second barrel shifter 205. When the bit lengths of the decoded code words added up in the adder 208a exceed the longest code word length, a carry is generated. This means that all the bits at storage in the interfacing first latch 202a have been transferred to the fifth latch 204b through the first barrel shifter 203. Because of this carry, all the bits in the third latch 202b are transferred to the second latch 202a, and the code words from the input buffer 201 are transferred to the interfacing second latch 202a. And, new 16 bit size data are simultaneously provided to the third latch 202b and the first barrel shifter 203 from the input buffer 201.
As has been explained, when implementing a high quality picture system, such as MPEG 1, NPEG 2, or HDTV, the variable length code decoder forms a function block, together with circuits around it connected thereto in many cases. And, though the outputs from the VLC table and decoded code bits may be directly stored in input buffers in function blocks different from each another, they are applied to circuits around the VLC table as input data or used as control signals for other function blocks in most cases. Therefore, it is necessary to decode bits of the code words in the shortest time while preventing the trouble from the longest delay time. In this case, the longest delay time of the function block in question exists in parts connecting the VLC decoder with circuits around it, rather than an internal circuit of the VLC decoder itself, which further causes the problem that limits a speed of a fast data transmission system as the circuits around it becomes complicated.
In the meantime, referring to the prior art variable length code decoder shown in FIG. 2, there is the problem that a greater sized VLC decoder is required because the interfacing first barrel shifter 203 and the decoding second barrel shifter 205 are required. Moreover, there has been the problem that a delay time exists in the parts connecting the VLC decoder to the circuits around it through the VLC table 206 and the decoding second barrel shifter 205.